A 10.31 ENOB 3.125 MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

A 12b-ENOB 61μW Noise-Shaping SAR ADC with a Passive Integrator

This paper presents a novel noise shaping SAR architecture that is simple, robust and low power. It is fully passive and only needs minor modification to a conventional SAR ADC. Through a passive integrator, quantization noise, comparator noise and DAC noise are shaped with a noise transfer function of (1 − 0.75z−1). Unlike conventional multi-bit deltasigma ADCs, both the noise transfer functio...

C18-2 A 13b-ENOB 173dB-FoM 2nd -Order NS SAR ADC with Passive Integrators

9.7-ENOB SAR ADC for Compressed Sensing

Moore’s law has allowed the microprocessor market to innovate at an astonishing rate. We believe microchip implants are the next frontier for the integrated circuit industry. Current health monitoring technologies are large, expensive, and consume significant power. By miniaturizing and reducing power, monitoring equipment can be implanted into the body and allow 24/7 health monitoring. We plan...

Very low power consumption SAR ADC for wireless sensor networks

This study aims to design analog-to-digital converter based on successive approximations (SAR ADC), with very low power consumption, in an advanced CMOS technology (28 nm), following the industrial methodologies IC. This project was conducted in partnership with Synopsys, operating at a supply voltage of 0.5 V ± 10% with a resolution of 12 bits and 500 kS/s sampling frequency. Keywords— Analog-...

Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PW...